1. Technical Field
The present disclosure relates to a pre-emphasis circuit and, more particularly, to a pre-emphasis circuit including a buffer capable of controlling the slew rate of an output signal.
2. Discussion of the Related Art
It is known that a transmitter can transmit two signals having a phase difference of 180° between them to a receiver to minimize the influence of noise introduced into the signals. The two signals form a specific eye pattern or eye diagram if the two signals overlap each other. This eye pattern is deformed when the signals are distorted due to noise introduced into the signals while the signals are transmitted. A signal is transmitted and received between the transmitter and the receiver via a transmission line. Frequently, a high-frequency component included in the transmitted/received signal will be cut off because the transmission line has a low pass band filter characteristic. The low pass filter characteristic of the transmission line is generally caused by interaction of a resistive component of the transmission line and a capacitive load existing between the transmission line and a ground voltage. Thus, the amplitude of the high-frequency component of the transmitted/received signal is reduced, while a low-frequency component thereof is not changed.
Since the high-frequency component of the transmitted/received signal is reduced, the eye pattern of the received signal is different from a normal eye pattern. That is, the received signal has a jitter component referred to as inter-symbol interference (ISI) jitter. To remove the ISI jitter, an operation of initially increasing the amplitude of the high-frequency component of the signal and transmitting the increased signal so that the original amplitude of the high-frequency component will be maintained even when it is reduced due to the low pass filter characteristic of the transmission line should be carried out. This amplitude increasing operation is referred to as pre-emphasis.
FIG. 1 illustrates a conventional pre-emphasis circuit. Referring to FIG. 1, the pre-emphasis circuit includes a first buffer 110, a second buffer 120, and an output driver 130. The first buffer 110 buffers two main signals having a phase difference of 180° between them and outputs first and second main signals VP and VN to the output driver 130. The second buffer 120 buffers two sub signals having a phase difference of 180° between them and outputs first and second sub-signals VP1 and VN1 to the output driver 130. The output driver 130 outputs two signals OUT and OUTB having a phase difference of 180° in response to the four signals VP, VN, VP1 and VN1. The amplitudes of the two signals OUT and OUTB are controlled by two control signals CON1 and CON2 fed to the output driver 130.
The first sub-signal VP1 is delayed from the first main signal VP by one bit and the second sub-signal VN1 is delayed from the second main signal VP by one bit.
FIG. 2 is a circuit diagram of the output driver 130 of FIG. 1. Referring to FIG. 2, the output driver 130 generates the signals OUT and OUTB having a phase difference of 180° between them in response to the four input signals VP, VN, VP1 and VN1. To pre-emphasize the signals OUT and OUTB, the currents flowing through two current sources Im and Is should be controlled using the two control signals CON1 and CON2. When the currents flowing through current sources Im and Is are controlled in multiple stages, pre-emphasis can be effectively performed to various degrees.
The frequency of a digital signal is reflected in the pulse width in the time domain. The frequency is high when the pulse width is narrow, and the frequency is low when the pulse width is wide. Accordingly, data having rapidly changing logic values becomes a high-frequency component and data having a more constant logic value becomes a low-frequency component.
FIG. 3 is a waveform diagram of signals of the output driver 130 of FIG. 2. FIG. 3 shows the second output voltage OUTB generated in response to the first main signal VP and the second sub signal VN1. The first sub signal VP1 is delayed from the first main signal VP by one bit and the first and second sub signals have a phase difference of 180° between them. When, as shown in FIG. 2, the first main signal VP and the second sub signal VN1 respectively applied to the gates of MOS transistors M1 and M3 are at a logic “1”, the voltage of the second output node OUTB is considerably increased, as shown at (2) in FIG. 3. When one of the first main signal VP and the second sub signal VN1 is at a logic “1” and the other one is at a logic “0”, the voltage of the second output node OUTB is only slightly increased, as shown at (1) in FIG. 3. When both the first main signal VP and the second sub signal VN1 are at a logic “0”, the voltage of the second output node OUTB is not changed, as shown at (0) in FIG. 3. The voltage of the first output node OUT has a phase opposite to the phase of the second output signal OUTB so that an explanation thereof is omitted.
The amplitudes of high-frequency components of the signals output from the first and second output nodes OUT and OUTB are reduced when the signals are transmitted via transmission lines. Thus, pre-emphasis for increasing the amplitudes of the high-frequency components is carried out on the signals before transmitting the signals via the transmission lines.
Referring to FIG. 3, the bold portions of the signal waveform of the second output node OUTB represent a high-frequency component whose amplitude should be increased. To increase the amplitude of the high-frequency component, it is required that many voltage steps be controlled by the control signals CON1 and CON2 used in the output driver 130 of FIG. 2. That is, the number of control signals should be increased. The range of voltage steps controllable by the control signals CON1 and CON2, however, is narrow when only the two control signals CON1 and CON2 are used in the output driver 130.